Open source projects
I started the PandA project in 2004. Within this framework I’m actively working on methodologies supporting high-level synthesis of hardware accelerators, on parallelism extraction for embedded systems, on hardware/software partitioning and mapping, on metrics for performance estimation of embedded software applications and on dynamic reconfigurable devices.
From time to time, I contributed to the FloPoCo project. FloPoCo is a generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only). FloPoCo has been even successfully integrated into the high-level synthesis tool bambu distributed with PandA framework.
European commission projects
I worked in these European funded projects as researcher:
- REQUEST – Reuse and quality estimation: advanced VHDL based design methodology for quick system development
- ICODES – Interface and Communication based Design of Embedded Systems
- hArtes – Holistic Approach to Reconfigurable Real Time Embedded Systems
- Synaptic – SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms
- Faster – Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
- SAVE – Self-Adaptive Virtualization-Aware High-Performance/Low-Energy Heterogeneous System Architectures
- HERMES-SP – High Energy Rapid Modular Ensemble of Satellites – Scientific Pathfinder
In addition, in Synaptic I worked as scientific coordinator for Politecnico di Milano.
European Space Agency projects
In the following ESA projects, I’ve worked as scientific coordinator/advisor:
- ESA/ESTEC/Contract N. 4000100797 – Development of methodologies and tools for predictable, real-time LEON-DSP based embedded systems.
- ESA/ESTEC/Contract No. 22167/09/NL/JK. Cache Optimization for LEON Analysis (COLA).
- ESA/ESTEC/Contract Call-Off Order 4 “Multicore and Schedulability Analysis” for TASTE project.
- ESA/ESTEC/Contract No. 4000121154/17/NL/LF Compact Reconfigurable Avionics Model Based Avionic Design (CORA-MBAD)
I coordinated in the context of “Progetto Giovani Ricercatori” the research titled “Definizione di una metodologia di collaudo per dispositivi elettronici descritti a livello algoritmico” and funded by Politecnico di Milano, 2000.
I was scientific coordinator for Politecnico di Milano of project “Nu-Specs (nu-tech speech engine with CUDA support)” – Bando 2008 giovane tecnologo-Intervento 1.1.1.04.03 – Marche innovazione
I’m Co-Principal Investigator on project “Design Automation for Data Analytics” accepted in the Intel Hardware Accelerator Research Program v2. Started 24-11-2016 and jointly developed with Pacific Northwest National Laboratory.
I’m Co-Principal Investigator on project “Hardware parallelization of cores accessing memory with irregular access patterns” accepted in the Intel Hardware Accelerator Research Program v2. Started 24-11-2016.