{"id":12,"date":"2013-07-24T16:30:06","date_gmt":"2013-07-24T15:30:06","guid":{"rendered":"http:\/\/pierofraternali.wordpress.com\/?page_id=12"},"modified":"2022-08-31T15:48:21","modified_gmt":"2022-08-31T14:48:21","slug":"projects","status":"publish","type":"page","link":"https:\/\/ferrandi.faculty.polimi.it\/?page_id=12","title":{"rendered":"[:en]Projects[:it]Progetti[:]"},"content":{"rendered":"<h2>Open source projects<\/h2>\n<p>I started the <a href=\"http:\/\/panda.dei.polimi.it\">PandA<\/a> project in 2004. Within this framework I&#8217;m actively working on methodologies supporting high-level synthesis of hardware accelerators, on parallelism extraction for embedded systems, on hardware\/software partitioning and mapping, on metrics for performance estimation of embedded software applications and on dynamic reconfigurable devices.<\/p>\n<p>From time to time, I contributed to the <a href=\"http:\/\/flopoco.gforge.inria.fr\/\">FloPoCo<\/a> project. FloPoCo is a generator of arithmetic cores (Floating-Point Cores, but not only) for FPGAs (but not only). FloPoCo has been even successfully integrated into the high-level synthesis tool bambu distributed with PandA framework.<\/p>\n<h2>European commission projects<\/h2>\n<p>I worked in these European funded projects as researcher:<\/p>\n<ul>\n<li><a href=\"http:\/\/cordis.europa.eu\/project\/rcn\/31625_en.html\" target=\"_blank\" rel=\"noopener noreferrer\">REQUEST<\/a> &#8211; Reuse and quality estimation: advanced VHDL based design methodology for quick system development<\/li>\n<li><a href=\"http:\/\/cordis.europa.eu\/project\/rcn\/71575_en.html\" target=\"_blank\" rel=\"noopener noreferrer\">ICODES<\/a> &#8211; Interface and Communication based Design of Embedded Systems<\/li>\n<li><a href=\"http:\/\/cordis.europa.eu\/project\/rcn\/79337_en.html\" target=\"_blank\" rel=\"noopener noreferrer\">hArtes<\/a> &#8211; Holistic Approach to Reconfigurable Real Time Embedded Systems<\/li>\n<li><a href=\"http:\/\/cordis.europa.eu\/project\/rcn\/93544_en.html\" target=\"_blank\" rel=\"noopener noreferrer\">Synaptic<\/a> &#8211; SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms<\/li>\n<li><a href=\"http:\/\/cordis.europa.eu\/project\/rcn\/99697_en.html\" target=\"_blank\" rel=\"noopener noreferrer\">Faster<\/a> &#8211; Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration<\/li>\n<li><a href=\"http:\/\/cordis.europa.eu\/project\/rcn\/109227_en.html\" target=\"_blank\" rel=\"noopener noreferrer\">SAVE<\/a> &#8211; Self-Adaptive Virtualization-Aware High-Performance\/Low-Energy Heterogeneous System Architectures<\/li>\n<li><a href=\"http:\/\/www.hermes-sp.eu\/\">HERMES-SP<\/a> &#8211; High Energy Rapid Modular Ensemble of Satellites &#8211; Scientific Pathfinder<\/li>\n<\/ul>\n<p>In addition, in Synaptic I worked as scientific coordinator for Politecnico di Milano.<\/p>\n<h2>European Space Agency projects<\/h2>\n<p>In the following ESA projects, I&#8217;ve worked as scientific coordinator\/advisor:<\/p>\n<ul>\n<li>ESA\/ESTEC\/Contract N. 4000100797 &#8211; Development of methodologies and tools for predictable, real-time LEON-DSP based embedded systems.<\/li>\n<li>ESA\/ESTEC\/Contract No. 22167\/09\/NL\/JK. Cache Optimization for LEON Analysis (COLA).<\/li>\n<li>ESA\/ESTEC\/Contract Call-Off Order 4 \u201cMulticore and Schedulability Analysis\u201d for <a href=\"http:\/\/taste.tuxfamily.org\/\" target=\"_blank\" rel=\"noopener noreferrer\">TASTE<\/a> project.<\/li>\n<li>ESA\/ESTEC\/Contract No. 4000121154\/17\/NL\/LF Compact Reconfigurable Avionics Model Based Avionic Design (CORA-MBAD)<\/li>\n<\/ul>\n<h2>National projects<\/h2>\n<p>I coordinated in the context of &#8220;Progetto Giovani Ricercatori&#8221; the research titled &#8220;Definizione di una metodologia di collaudo per dispositivi elettronici descritti a livello algoritmico&#8221; and funded by Politecnico di Milano, 2000.<\/p>\n<p>I was scientific coordinator for Politecnico di Milano of project &#8220;Nu-Specs (nu-tech speech engine with CUDA support)&#8221; &#8211; Bando 2008 giovane tecnologo-Intervento 1.1.1.04.03 &#8211; Marche innovazione<\/p>\n<h2>Other Projects<\/h2>\n<p>I&#8217;m Co-Principal Investigator on project &#8220;Design Automation for Data Analytics&#8221; accepted in the <a href=\"https:\/\/www.sigarch.org\/2016\/09\/28\/call-for-submissions-intel-hardware-accelerator-research-program-v2\">Intel Hardware Accelerator Research Program v2<\/a>. Started 24-11-2016 and jointly developed with <a href=\"https:\/\/www.pnl.gov\/\">Pacific Northwest National Laboratory<\/a>.<\/p>\n<p>I&#8217;m Co-Principal Investigator on project &#8220;Hardware parallelization of cores accessing memory with irregular access patterns&#8221; accepted in the <a href=\"https:\/\/www.sigarch.org\/2016\/09\/28\/call-for-submissions-intel-hardware-accelerator-research-program-v2\">Intel Hardware Accelerator Research Program v2<\/a>. Started 24-11-2016.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Open source projects I started the PandA project in 2004. Within this framework I&#8217;m actively working on methodologies supporting high-level synthesis of hardware accelerators, on parallelism extraction for embedded systems, on hardware\/software partitioning and mapping, on metrics for performance estimation of embedded software applications and on dynamic reconfigurable devices. From time to time, I contributed &hellip; <a href=\"https:\/\/ferrandi.faculty.polimi.it\/?page_id=12\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">[:en]Projects[:it]Progetti[:]<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":3,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-12","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/12","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=12"}],"version-history":[{"count":22,"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/12\/revisions"}],"predecessor-version":[{"id":254,"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/12\/revisions\/254"}],"wp:attachment":[{"href":"https:\/\/ferrandi.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=12"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}